Two-stage channel routing for CMOS gate arrays

A two-stage channel routing technique for CMOS gate arrays is proposed. In the first stage, certain nets are routed on two sides of the channel so that channel density is reduced. A single-side O(N ) optimum algorithm is presented for this stage. The algorithm can choose one set with maximum weight from among the possible sets of routing nets. The second stage can be general channel routing. An efficient algorithm for one-and-a-half-layer routing model that is based on one metal mask and a fixed poly-crossunder layer is presented. This router scans the channel in a left-to-right, zone-by-zone manner, using a multilevel prediction to guide wiring and a greedy approach for nets to contend for limited crossunders. Implementation results are provided to indicate the efficiency of the technique