Improvement on a block-serial fully-overlapped QC-LDPC decoder for IEEE 802.11n

This paper presents a block-serial fully-overlapped Quasi-Cyclic Low Density Parity Check (QC-LDPC) decoder for IEEE 802.11n. Based on the circuit retiming and message bypassing techniques, this decoder effectively improved the previous work proposed by Xiang et al. with an 11% clock-rate increase and a 3% decoding time reduction on average. Moreover, the proposed chip spends about 3.67 mm in 90 nm CMOS technology, its power approximately consumes 171 mW at 250 MHz, and throughput of the proposed design can reach 672 Mbps.