A CMOS-compatible complementary SINFET HVIC process

Author

Ng, W.T. ; Salama, C. Andre T

Author_Institution

Dept. of Electr. Eng., Toronto Univ., Ont., Canada

Volume

38

Issue

8

fYear

1991

fDate

8/1/1991 12:00:00 AM

Firstpage

1935

Lastpage

1942

Abstract

A CMOS-compatible complementary SINFET (Schottky injection field effect transistors) process is described. The high speed n- and p-channel SINFETs use Schottky-barrier injectors to provide higher current handling capability than presently available in a CMOS-compatible HVIC environment. Schottky-barrier height enhancement implants are used to optimize the injection level in the SINFETs n- and p-buried layers which are used for breakdown control and isolation. Low-voltage CMOS control circuits and complementary merged MOS-bipolar output devices with current sourcing and sinking capabilities can be fabricated using the process

Keywords

CMOS integrated circuits; integrated circuit technology; power integrated circuits; CMOS-compatible; Schottky injection field effect transistors; Schottky-barrier injectors; breakdown control; complementary SINFET HVIC process; current handling capability; current sourcing; height enhancement implants; injection level; n-channel SINFETs; p-channel SINFETs; sinking capabilities; CMOS process; CMOS technology; Degradation; Driver circuits; Electric breakdown; Environmental economics; Implants; Integrated circuit technology; Production; Signal processing;

fLanguage

English

Journal_Title

Electron Devices, IEEE Transactions on

Publisher

ieee

ISSN

0018-9383

Type

jour

DOI

10.1109/16.119036

Filename

119036