A 5.2-GHz LNA in 0.35-μm CMOS utilizing inter-stage series resonance and optimizing the substrate resistance

Author

Cha, Choong-Yul ; Lee, Sang-Gug

Author_Institution

Sch. of Eng., Inf. & Commun. Univ., Daejeon, South Korea

Volume

38

Issue

4

fYear

2003

fDate

4/1/2003 12:00:00 AM

Firstpage

669

Lastpage

672

Abstract

A current-reused two-stage low-noise amplifier (LNA) topology is proposed, which adopts a series inter-stage resonance and optimized substrate resistance of individual transistors. The characteristics of the series inter-stage resonance in gain enhancement are analyzed and compared with other alternatives. The contradicting effects of substrate resistance on common-source and common-gate amplifiers are analyzed and proposed guidelines for high-gain operation. The LNA is implemented based on a 0.35-μm CMOS technology for 5.2-GHz wireless LAN applications. Measurements show 19.3dB of power gain, 2.45 dB of noise figure, and 13.2 dBm of output IP3, respectively, for the dc power supply of 8 mA and 3.3 V.

Keywords

CMOS analogue integrated circuits; circuit resonance; radiofrequency amplifiers; radiofrequency integrated circuits; wireless LAN; 0.35 micron; 19.3 dB; 2.45 dB; 3.3 V; 5.2 GHz; 8 mA; RF CMOS LNA; common-gate amplifier; common-source amplifier; current-reused two-stage low-noise amplifier; inter-stage series resonance; noise figure; output IP3; power gain; substrate resistance; wireless LAN; CMOS technology; Electrical resistance measurement; Gain measurement; Guidelines; Low-noise amplifiers; Operational amplifiers; Power measurement; Resonance; Topology; Wireless LAN;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/JSSC.2003.809523

Filename

1190604