A modified novel compressor based Urdhwa Tiryakbhyam multiplier

Author

Rajasekhar, N. ; Shanmuganantham, T.

Author_Institution

Dept. of Electron. Eng., Pondicherry Univ., Pondicherry, India

fYear

2014

fDate

3-5 Jan. 2014

Firstpage

1

Lastpage

5

Abstract

With the advent of new technology in the domain of VLSI, communication and signal processing, there is an ever going demand for the high speed processing and low area design. In this paper, introduces modified compressor based multiplier architecture. This modified structure uses the 4:2 compressor and 7:2 compressor architectures. In addition to that it uses Vedic mathematics to get a high speed multiplication operation and low area design. The design and experiments carried were carried out on a Xilinx Spartan 3E series of FPGA and discussed about the results of area and speed.

Keywords

VLSI; field programmable gate arrays; logic design; multiplying circuits; FPGA; Urdhwa Tiryakbhyam multiplier; VLSI; Vedic mathematics; Xilinx Spartan 3E series; communication; compressor; signal processing; Adders; Computer architecture; Computers; Hardware; Informatics; Logic gates; Mathematics; 4∶2 compressor; 7∶2 compressor; High speed multiplier; modified architecture; vedic mathematics;

fLanguage

English

Publisher

ieee

Conference_Titel

Computer Communication and Informatics (ICCCI), 2014 International Conference on

Conference_Location

Coimbatore

Print_ISBN

978-1-4799-2353-3

Type

conf

DOI

10.1109/ICCCI.2014.6921784

Filename

6921784