Title :
Parallel architecture for high-speed Viterbi decoding of convolutional codes
Author :
Zhang, Y.F. ; Csillag, P.
Author_Institution :
GAPSE/ENDEEIHT, Toulouse, France
fDate :
7/6/1989 12:00:00 AM
Abstract :
A parallelisation algorithm of decoding convolutional codes with the Viterbi algorithm is presented. The architecture of parallel decoding analysed here suits the VLSI realisation very well and allows high-speed decoding.
Keywords :
VLSI; decoding; digital integrated circuits; parallel architectures; VLSI realisation; Viterbi algorithm; convolutional codes; decoding convolutional codes; high-speed Viterbi decoding; high-speed decoding; parallel architecture; parallelisation algorithm;
Journal_Title :
Electronics Letters
DOI :
10.1049/el:19890595
