DocumentCode :
1170884
Title :
Routability-driven white space allocation for fixed-die standard-cell placement
Author :
Yang, Xiaojian ; Choi, Bo-Kyung ; Sarrafzadeh, Majid
Author_Institution :
Synplicity Inc., Sunnyvale, CA, USA
Volume :
22
Issue :
4
fYear :
2003
fDate :
4/1/2003 12:00:00 AM
Firstpage :
410
Lastpage :
419
Abstract :
The use of white space in fixed-die standard-cell placement is an effective way to improve routability. In this paper, we present a white space allocation approach that dynamically assigns white space according to the congestion distribution of the placement. In the top-down placement flow, white space is assigned to congested regions using smooth allocating functions. A post-allocation optimization step is taken to further improve placement quality. Experimental results show that the proposed allocation approach, combined with a multilevel placement flow, significantly improves placement routability and layout quality. A set of approaches for white space allocation has been presented and compared in this paper. All of them are based on routability-driven methods. However, these approaches vary in the allocation function and allocation aggressiveness. All the placement results are investigated by feeding them into a widely used industrial router (Warp Route of Cadence). Comparisons have been made between: 1) placement with or without white space allocation; 2) different white space allocation approaches; and 3) our placement flow, industrial placement tool, and the other state-of-the-art academic placement tool.
Keywords :
VLSI; cellular arrays; circuit layout CAD; circuit optimisation; integrated circuit layout; network routing; Cadence Warp Route; dynamic assignment; fixed-die standard-cell placement; industrial router; layout quality; multilevel placement flow; placement congestion distribution; placement routability improvement; post-allocation optimization step; routability-driven white space allocation; smooth allocating functions; top-down placement flow; Aerospace industry; Analytical models; Computational modeling; Computer science; Data structures; Routing; Simulated annealing; Terrorism; White spaces; Wires;
fLanguage :
English
Journal_Title :
Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on
Publisher :
ieee
ISSN :
0278-0070
Type :
jour
DOI :
10.1109/TCAD.2003.809660
Filename :
1190978
Link To Document :
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