Title :
Buffer tree synthesis with consideration of temporal locality, sink polarity requirements, solution cost, congestion, and blockages
Author :
Hrkic, Milos ; Lillis, John
Author_Institution :
Dept. of Comput. Sci., Univ. of Illinois, Chicago, IL, USA
fDate :
4/1/2003 12:00:00 AM
Abstract :
We give an overview of a buffer tree synthesis package which pays particular attention to the following issues: routing and buffer blockages, minimization of interconnect and buffer costs, congestion, exploitation of temporal locality among the sinks, and addressing sink polarity requirements. Experimental results demonstrate the effectiveness of the tool in comparison with previously proposed techniques.
Keywords :
buffer circuits; circuit layout CAD; computational complexity; integrated circuit interconnections; integrated circuit layout; network routing; timing; trees (mathematics); Steiner trees; buffer blockages; buffer cost minimization; buffer insertion; buffer tree synthesis package; buffered interconnects synthesis; interconnect cost minimization; routing; timing optimization; Circuit topology; Costs; Councils; Dynamic programming; Engineering profession; Heuristic algorithms; Packaging; Routing; Timing; Wire;
Journal_Title :
Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on
DOI :
10.1109/TCAD.2003.809648
