Title :
Buffer insertion with adaptive blockage avoidance
Author :
Hu, Jiang ; Alpert, Charles J. ; Quay, Stephen T. ; Gandham, Gopal
Author_Institution :
Dept. of Electr. Eng., Texas A&M Univ., College Station, TX, USA
fDate :
4/1/2003 12:00:00 AM
Abstract :
Buffer insertion is a fundamental technology for very large scale integration interconnect optimization. This work presents the repeater insertion with adaptive tree adjustment (RIATA) heuristic that directly extends van Ginneken´s classic algorithm to handle blockages in the layout. Given a Steiner tree containing a Steiner point that overlaps a blockage, a local adjustment is made to the tree topology that enables additional buffer insertion candidates to be considered. This adjustment adapts to the demand on buffer insertion and is incurred only when it facilitates the maximal slack solution. RIATA can be combined with any performance-driven Steiner tree algorithm and permits various solution search schemes to achieve different solution quality and runtime tradeoffs. Experiments on several large nets confirms that high-quality solutions can be obtained through this technique with greater efficiency than simultaneous approaches.
Keywords :
VLSI; circuit layout CAD; circuit optimisation; integrated circuit interconnections; integrated circuit layout; trees (mathematics); RIATA; Steiner tree; adaptive blockage avoidance; adaptive tree adjustment; buffer insertion; heuristic; interconnect optimization; local adjustment; maximal slack solution; repeater insertion; runtime tradeoffs; solution quality; solution search schemes; van Ginneken´s classic algorithm; very large scale integration; Delay; Heuristic algorithms; Law; Legal factors; Repeaters; Runtime; Timing; Topology; Very large scale integration; Wires;
Journal_Title :
Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on
DOI :
10.1109/TCAD.2003.809647