Very-high-speed VLSI 2s-complement multiplier using signed binary digits

A high-speed 8*8-bit multiplier design for 2s-complement binary numbers is presented. The multiplier uses the binary signed-digit number system to achieve both high speed and layout simplicity, and is implemented in double layer metal 2 mu m CMOS technology. The multiplication time for the array was found by simulation to be 18 ns at 25 degrees C and its size was measured as 1.7 mm*2.3 mm (excluding pads). Power dissipation was calculated as just less than 40 mW at 55 MHz, and the transistor count is 3754 transistors.