A low power double phase clock multiband flexible divider

Clock consumes mostly 60% of the maximum power in an IC since it is the single signal which propagate to all part of the design with maximum toggling rate so it should be taken at most care for designing a multiband low power clock. Affiliated standards are the Wireless LAN (WLAN) in the multigigahertz bands such as HiperLAN II and IEEE 802.11a/b/g, for higher end data link and standards like IEEE 802.15.4 are affiliated for low-rate data communication. The demand for cheaper cost, cheaper power and multiband RF designs increased in connection with need of maximum level of integration. In this Project IEEE 802.15.4 and 802.11 a/b/g WLAN frequency synthesizer is designed based on pulse-swallow topology and it is simulated using Verilog HDL, Modelism and Synthesized using Tanner tool. The complex band divider contain a wideband multimodulus 32/33/47/48 frequecy divider and an developed unit-cell for swallow (S) counter and can separate the frequencies in the three bands of 2.4-2.484 GHz, 5.15-5.35 GHz, and 5.725-5.825 GHz with a resolution selectable from 1 to 25 MHzThis design aims for designing a low power double clock for multiband frequency. The design is modeled using Verilog, simulated using Modelism and synthesized using Tanner.