• DocumentCode
    1171191
  • Title

    A priori wire length distribution models with multiterminal nets

  • Author

    Stroobandt, Dirk

  • Author_Institution
    RUG-ELIS Dept., Ghent Univ., Belgium
  • Volume
    11
  • Issue
    1
  • fYear
    2003
  • Firstpage
    35
  • Lastpage
    43
  • Abstract
    Interconnections are quickly becoming a dominant factor in the design of computer chips. Techniques to estimate interconnection lengths a priori (very early in the design flow) therefore gain attention and will become important for making the right design decisions when one still has the freedom to do so. However, at that time, one also knows least about the possible results of subsequent design steps. Conventional models for a priori estimation of wire lengths in computer chips use Rent´s rule to estimate the number of terminals needed for communication between sets of gates. The number of interconnections then follows by taking into account that most nets are point-to-point connections. In this paper, we apply our previously introduced model for multiterminal nets to show that such nets have a fundamentally different influence on the wire length estimations than point-to-point nets. We then estimate the wire length distribution of Steiner tree lengths for applications related to routing resource estimation. Experiments show that the new estimated Steiner-length distributions capture the multiterminal effects much better than the previous point-to-point length distributions. The accuracy of the estimated values is still too low, as for the conventional point-to-point models, because we are still lacking a good model for placement optimization. However, the new results are a step closer to the application of wire length estimation techniques in real-world situations.
  • Keywords
    VLSI; estimation theory; integrated circuit interconnections; integrated circuit layout; integrated circuit modelling; multiterminal networks; network routing; trees (mathematics); Rent´s rule; Steiner tree lengths; VLSI chips; a priori models; computer chips; interconnections; multiterminal nets; routing resource estimation; wire length distribution models; wire length estimations; Application software; Circuit topology; Delay; Integrated circuit interconnections; Predictive models; Routing; Very large scale integration; Wire; Wiring;
  • fLanguage
    English
  • Journal_Title
    Very Large Scale Integration (VLSI) Systems, IEEE Transactions on
  • Publisher
    ieee
  • ISSN
    1063-8210
  • Type

    jour

  • DOI
    10.1109/TVLSI.2003.810002
  • Filename
    1191313