Wiring requirement and three-dimensional integration technology for field programmable gate arrays

Author

Rahman, Arifur ; Das, Shamik ; Chandrakasan, Anantha P. ; Reif, Rafael

Author_Institution

Polytech. Univ., Brooklyn, NY, USA

Volume

11

Issue

1

fYear

2003

Firstpage

44

Lastpage

54

Abstract

In this paper, analytical models for predicting interconnect requirements in field-programmable gate arrays (FPGAs) are presented, and opportunities for three-dimensional (3-D) implementation of FPGAs are examined. The analytical models for two-dimensional FPGAs are calibrated by routing and placement experiments with benchmark circuits and extended to 3-D FPGAs. Based on system-level modeling, we find that in FPGAs with more than 20 K four-input look-up tables, the reduction in channel width, interconnect delay and power dissipation can be over 50% by 3-D implementation.

Keywords

VLSI; delay estimation; field programmable gate arrays; integrated circuit interconnections; integrated circuit layout; integrated circuit modelling; integrated circuit technology; logic design; network routing; stochastic processes; 3D FPGAs; 3D ICs; 3D integrated circuit; 3D integration technology; Rent´s rule; analytical models; channel width reduction; field-programmable gate arrays; four-input look-up tables; interconnect delay; interconnect delay reduction; interconnect requirements; placement experiments; power dissipation reduction; routability prediction; routing experiments; stochastic models; system-level modeling; three-dimensional integration technology; wiring requirement; Delay; Field programmable gate arrays; Integrated circuit interconnections; Power dissipation; Power system interconnection; Programmable logic arrays; Programmable logic devices; Three-dimensional integrated circuits; Wafer bonding; Wiring;

fLanguage

English

Journal_Title

Very Large Scale Integration (VLSI) Systems, IEEE Transactions on

Publisher

ieee

ISSN

1063-8210

Type

jour

DOI

10.1109/TVLSI.2003.810003

Filename

1191315