DocumentCode :
1171250
Title :
Noise-aware interconnect power optimization in domino logic synthesis
Author :
Kim, Ki-Wook ; Jung, Seong-Ook ; Narayanan, Unni ; Liu, C.L. ; Kang, Sung-Mo
Author_Institution :
Brocade Commun. Syst. Inc., San Jose, CA, USA
Volume :
11
Issue :
1
fYear :
2003
Firstpage :
79
Lastpage :
89
Abstract :
Realization of high-performance domino logic depends strongly on energy-efficient and noise-tolerant interconnect design in ultradeep submicrometer processes. We characterize the cycle-averaged power model for interconnects accounting for switching statistics and dynamic behaviors. For the sake of signal integrity, cross-coupling effects are also characterized, which reflect logical correlation between adjacent wires. Based on the new models for interconnect power and capacitive crosstalk, we optimize the coupling power consumed by interconnects with crosstalk constraints. Experimental results show that optimized designs save the power consumption about 14% on average.
Keywords :
VLSI; capacitance; circuit optimisation; crosstalk; delay estimation; integrated circuit modelling; integrated circuit noise; integrated logic circuits; logic CAD; network routing; probability; capacitive crosstalk model; cross-coupling effects; crosstalk constraints; cycle-averaged power model; domino logic synthesis; dual threshold voltage; dynamic behaviour; energy-efficient interconnect design; high-performance domino logic; interconnect power model; noise-aware interconnect power optimization; noise-tolerant interconnect design; signal integrity; switching statistics; transistor sizing; ultradeep submicron processes; Capacitance; Crosstalk; Delay effects; Logic design; Packaging; Power dissipation; Power system interconnection; Semiconductor device noise; Threshold voltage; Wire;
fLanguage :
English
Journal_Title :
Very Large Scale Integration (VLSI) Systems, IEEE Transactions on
Publisher :
ieee
ISSN :
1063-8210
Type :
jour
DOI :
10.1109/TVLSI.2002.801630
Filename :
1191324
Link To Document :
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