Title :
Capacitance scaling aware power optimized register design and implementation on 28nm FPGA
Author :
Banshal, Sumit Kumar ; Pandey, Bishwajeet ; Brenda, S.J.
Author_Institution :
Dept. Of Comput. Sci., South Asian Univ., New Delhi, India
Abstract :
Power optimization is the main concern in designing. In this paper, capacitance scaling is implemented on register to optimize the power. Clock Power & Signal Power are independent of capacitance scaling. I/O Power & Leakage Power is varying with changing capacitance. There is 48.76% drop in I/O Power when we reduce capacitance from 512 pF to 256 pF. In case of reducing further to 128 pF there is 73.15% power reduction occurred. To go more further to reduce capacitance to 64 pF the reduction scale is going up to 85.34%. When we reduce the capacitance to 32 pF the reduction in power dissipation is 97.00%. This design is implemented on 28 nm Artix7 FPGA. The power consumption of this design is verified on XPower 14.6.
Keywords :
capacitance measurement; circuit optimisation; field programmable gate arrays; flip-flops; low-power electronics; Artix7 FPGA; I/O power; XPower 14.6; capacitance reduction; capacitance scaling; leakage power; power consumption; power dissipation reduction; power optimization; size 28 nm; Capacitance; Clocks; Field programmable gate arrays; Optimization; Power demand; Power dissipation; Registers; Capacitance Scaling; Energy Efficient; Power Optimization; Processor Register;
Conference_Titel :
Computer Communication and Informatics (ICCCI), 2014 International Conference on
Conference_Location :
Coimbatore
Print_ISBN :
978-1-4799-2353-3
DOI :
10.1109/ICCCI.2014.6921838
