A content addressable memory management unit with on-chip data cache

Author

Goksel, A. Kemal ; Krambeck, Robert H. ; Thomas, Phillip P. ; Tsay, Mean-sea ; Chen, Cheng Yueh ; Clemons, Donald G. ; LaRocca, Frank D. ; Mai, Liang-Peng

Author_Institution

AT&T Bell Lab., Holmdel, NJ, USA

Volume

24

Issue

3

fYear

1989

fDate

6/1/1989 12:00:00 AM

Firstpage

592

Lastpage

596

Abstract

The design of a single chip (WE-32201) that includes both a content-addressable memory-based management unit and a large data/instruction cache is described. The chip belongs to AT&T´s WE-32200 chip set and is fabricated using a 1 μm twin tub CMOS process. It boosts the performance of the entire chip set significantly by providing high memory bandwidth and virtual-memory-management support. The combination of high-performance circuit design and system architectural design techniques makes the chip a major enhancement to the chip set

Keywords

CMOS integrated circuits; buffer storage; content-addressable storage; storage management chips; 1 micron; AT&T; CAM based unit; MMU; WE-32200 chip set; WE-32201; content addressable memory; data/instruction cache; memory management unit; onchip data cache; single chip; twin tub CMOS process; virtual-memory-management support; Associative memory; Bandwidth; CADCAM; Circuit synthesis; Computer aided manufacturing; Content management; Laboratories; Memory management; Microprocessors; Protocols;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/4.32012

Filename

32012