DocumentCode :
1171732
Title :
Postroute gate sizing for crosstalk noise reduction
Author :
Becer, Murat R. ; Blaauw, David ; Algor, Ilan ; Panda, Rajendran ; Oh, Chanhee ; Zoloto, Vladimir Zoloto ; Hajj, Ibrahim N.
Author_Institution :
Freescale Semicond., Austin, TX, USA
Volume :
23
Issue :
12
fYear :
2004
Firstpage :
1670
Lastpage :
1677
Abstract :
Gate sizing is a practical and a feasible crosstalk noise correction technique in the post route design stage, especially for block level sea-of-gates designs. The difficulty in gate sizing for noise reduction is that, by increasing a driver size, noise at the driver output is reduced, but noise injected by that driver on other nets is increased. This can create cyclical dependencies between nets in the circuit with noise violations. In this paper, we propose a fast and effective heuristic postroute gate-sizing algorithm that uses a graph representation of the noise dependencies between nodes. Our method utilizes gate sizing in both directions and works in linear time as a function of the number of gates. The effectiveness of the algorithm is shown on several industrial high-performance designs.
Keywords :
circuit optimisation; crosstalk; graph theory; integrated circuit layout; integrated circuit noise; logic arrays; logic design; logic gates; network routing; block level sea-of-gates design; crosstalk noise reduction; driver output noise; driver size; graph representation; noise dependencies; noise repair; noise violations; post route design; postroute gate sizing; signal integrity; Algorithm design and analysis; Capacitance; Circuit noise; Coupling circuits; Crosstalk; Delay; Driver circuits; Noise reduction; Semiconductor device noise; Wire; 65; Crosstalk noise; gate sizing; noise repair; signal integrity;
fLanguage :
English
Journal_Title :
Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on
Publisher :
ieee
ISSN :
0278-0070
Type :
jour
DOI :
10.1109/TCAD.2004.836736
Filename :
1362737
Link To Document :
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