• DocumentCode
    1171749
  • Title

    Retiming-based timing analysis with an application to mincut-based global placement

  • Author

    Cong, J. ; Sung Kyu Lim

  • Author_Institution
    Dept. of Comput. Sci., Univ. of California, Los Angeles, CA, USA
  • Volume
    23
  • Issue
    12
  • fYear
    2004
  • Firstpage
    1684
  • Lastpage
    1692
  • Abstract
    In this paper, we formulate the physical planning with retiming problem and propose an algorithm called GEO. Our performance-driven global placement algorithm GEO is mincut-based, where a multilevel partitioning is performed recursively to divide the netlist and assign gates to the tiles in a top-down fashion. The contribution of our work is on the development of retiming-aware timing analysis (RTA) that is used to guide our mincut-based global placement. Compared to the conventional static timing analysis, RTA provides timing slack information after retiming so that the clock period after retiming can be directly minimized during the placement. We show how to make an effective use of RTA timing slack information in a multilevel partitioning framework. Simultaneous consideration of partitioning and retiming under the geometric delay model enables GEO to hide global interconnect latency more effectively compared to the conventional approaches. In our comparison to the state-of-the art methods that perform partitioning, retiming, and simulated annealing-based floorplanning separately, GEO obtains significant improvement on retimed delay, while maintaining comparable wirelength and runtime results.
  • Keywords
    circuit layout; circuit optimisation; integrated circuit design; integrated circuit interconnections; logic partitioning; simulated annealing; statistical analysis; GEO; clock period; floorplanning; geometric delay model; global interconnect latency; global placement algorithm; mincut-based global placement; multilevel partitioning framework; physical planning; retiming-aware timing analysis; simulated annealing; static timing analysis; timing slack information; Delay effects; Information analysis; Partitioning algorithms; Runtime; Simulated annealing; Solid modeling; Timing; Global placement; retiming-based timing analysis;
  • fLanguage
    English
  • Journal_Title
    Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on
  • Publisher
    ieee
  • ISSN
    0278-0070
  • Type

    jour

  • DOI
    10.1109/TCAD.2004.837718
  • Filename
    1362739