High-frequency phase-locked loops in monolithic bipolar technology

Circuit design techniques for realizing high-frequency, low-power phase-locked loops (PLLs) in monolithic silicon bipolar technology are discussed. A varactor-tuned voltage-controlled oscillator (VCO), an analog phase detector, and a bandgap reference have been utilized as building blocks. A test circuit fabricated in a 2-μm bipolar process exhibited a maximum center frequency of 350 MHz, and the PLL pull-in range was larger than ±1%. The circuit operates from a 5-V supply and dissipates 270 mW