Title :
A fine-line NMOS 3-Gbit/s 12 channel time-division multiplexer-demultiplexer chip set
Author :
Bayruns, Robert J. ; Hofstatter, Elizabeth A. ; Weston, Harry T.
Author_Institution :
AT&T Bell Lab., Murray Hill, NJ, USA
fDate :
6/1/1989 12:00:00 AM
Abstract :
A 12:1 multiplexer and 11:2 demultiplexer that operate at up to 3 Gb/s are discussed. The circuits were fabricated with a 1-μm-design-rule silicon NMOS VLSI technology and operate from a 3.5-V power supply. The multiplexer chip has 200 gates and dissipates 0.5 W of power. The demultiplexer chip has 400 gates and dissipates 0.75 W. Performance of these devices compares well in both speed and power to the best gallium-arsenide results reported to date
Keywords :
MOS integrated circuits; VLSI; multiplexing equipment; 0.5 W; 0.75 W; 1 micron; 12 channel time-division multiplexer-demultiplexer chip set; 3 Gbit/s; 3.5 V; NMOS VLSI technology; Si; Clocks; Counting circuits; Gallium arsenide; Latches; Logic circuits; MOS devices; Multiplexing; Shift registers; Silicon; Very large scale integration;
Journal_Title :
Solid-State Circuits, IEEE Journal of
