Characteristics of body-tied triple-gate pMOSFETs

Author

Park, Tai-Su ; Cho, Hye Jin ; Choe, Jeong Dong ; Cho, Il Hwan ; Park, Donggun ; Yoon, Euijoon ; Lee, Jong Ho

Author_Institution

Sch. of Mater. Sci. & Eng., Seoul Nat. Univ., South Korea

Volume

25

Issue

12

fYear

2004

Firstpage

798

Lastpage

800

Abstract

Body-tied triple-gate pMOSFETs were fabricated using bulk Si wafers and characterized. Process steps to implement the devices are explained briefly. Device characteristics of the triple-gate pMOSFETs were compared with those of the conventional planar channel device. While maintaining low off-leakage currents and threshold voltages similar to those of planar pMOSFETs in the parallel arrayed 30 000 transistors, the body-tied triple-gate MOSFETs showed about 74 mV/dec of subthreshold swing (92 mV/dec for conventional devices) and a drain-induced barrier lowering of 34 mV/V (92 mV/V for conventional devices). It was also addressed that I_SUB/I_D of the body-tied triple-gate is lower than that of the planar channel device.

Keywords

MOSFET; field effect transistors; leakage currents; FinFET; Si; body-tied triple-gate pMOSFET; bulk Si wafers; drain-induced barrier; low off-leakage currents; parallel arrayed transistors; planar channel device; planar pMOSFET; subthreshold swing; threshold voltages; CMOS technology; Etching; FinFETs; Hafnium; Lithography; MOSFETs; Random access memory; Resists; Silicon compounds; Silicon on insulator technology; 65; Body-tied; FinFET; bulk; omega; triple-gate;

fLanguage

English

Journal_Title

Electron Device Letters, IEEE

Publisher

ieee

ISSN

0741-3106

Type

jour

DOI

10.1109/LED.2004.838060

Filename

1362779