DocumentCode :
117259
Title :
An FPGA co-processor implementation of Homomorphic Encryption
Author :
Cousins, David Bruce ; Golusky, John ; Rohloff, Kurt ; Sumorok, Daniel
Author_Institution :
Raytheon BBN Technol., Cambridge, MA, USA
fYear :
2014
fDate :
9-11 Sept. 2014
Firstpage :
1
Lastpage :
6
Abstract :
One of the goals of the DARPA PROCEED program has been accelerating the development of a practical Fully Homomorphic Encryption (FHE) scheme. For the past three years, this program has succeeded in accelerating various aspects of the FHE concept toward practical implementation and use. FHE is a game-changing technology to enable secure, general computation on encrypted data on untrusted off-site hardware, without the data ever being decrypted for processing. FHE schemes developed under PROCEED have achieved multiple orders of magnitude improvement in computation, but further means of acceleration, such as implementations on specialized hardware, such as an FPGA can improve the speed of computation even further. The current interest in FHE computation resulted from breakthroughs demonstrating the existence of FHE schemes [1, 2] that allowed arbitrary computation on encrypted data. Specifically, our contribution to the Proceed program has been the development of FPGA based hardware primitives to accelerate the computation on encrypted data using an FHE cryptosystem based on NTRU-like lattice techniques [3] with additional with additional support for efficient key switching and modulus reduction operations to reduce the frequency of bootstrapping operations [4]. Cipher texts in our scheme are represented as rectangular matrices of 64-bit integers. This bounding of the oper-and sizes has allowed us to take advantage of modern code generation tools developed by Mathworks to implement VHDL code for FPGA circuits directly from Simulink models. Furthermore the implicit parallelism of the scheme allows for large amounts of pipelining in the implementation in order to achieve efficient throughput. The resulting VHDL is integrated into an AXI4 bus “Soft System on Chip” using Xilinx platform studio and a Microblaze soft core processor running on a Virtex7 VC707 evaluation board. This report presents new Simulink primitives that had to be developed to deal with - hese new requirements.
Keywords :
coprocessors; cryptography; field programmable gate arrays; hardware description languages; matrix algebra; system-on-chip; AXI4 bus; DARPA PROCEED program; FHE cryptosystem; FHE scheme; FPGA based hardware primitives; FPGA circuits; FPGA co-processor implementation; Mathworks; Microblaze soft core processor; NTRU-like lattice techniques; Simulink models; VHDL code; Virtex7 VC707 evaluation board; Xilinx platform studio; bootstrapping operations; cipher texts; code generation tools; fully homomorphic encryption scheme; key switching; modulus reduction operations; rectangular matrices; soft system on chip; specialized hardware; word length 64 bit; Ciphers; Encryption; Field programmable gate arrays; Noise; Poles and towers; Registers; Co-processor; FPGA; Fully Homomorphic Encryption; SIMULINK;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
High Performance Extreme Computing Conference (HPEC), 2014 IEEE
Conference_Location :
Waltham, MA
Print_ISBN :
978-1-4799-6232-7
Type :
conf
DOI :
10.1109/HPEC.2014.7040950
Filename :
7040950
Link To Document :
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