Synchronization design of a coupled phase-locked loop

Author

Buckwalter, James F. ; Heath, Ted H. ; York, Robert A.

Author_Institution

Dept. of Electr. & Comput. Eng., Univ. of California, Santa Barbara, CA, USA

Volume

51

Issue

3

fYear

2003

fDate

3/1/2003 12:00:00 AM

Firstpage

952

Lastpage

960

Abstract

Coupled phase-locked loops (CPLLs) are introduced as novel circuits for phased-array antennas. Successful implementation relies on characterizing the synchronization behavior of CPLL circuits over a broad range of circuit parameters. Considering inherent time delay in the phase-locked loop demonstrates the degradation in the pull-in and hold-in ranges, as well as circuit instabilities, suggesting circuit parameter limits in a phased-array design. We compare the theoretical limits, in the form of analytic equations and numerical simulations, with measurements of the pull-in and hold-in processes of a 1.5-GHz prototype CPLL.

Keywords

UHF antennas; antenna phased arrays; circuit stability; coupled circuits; network parameters; phase locked loops; 1.5 GHz; CPLLs; analytic equations; circuit instabilities; circuit parameter limits; circuit parameters; coupled phase-locked loop; hold-in range; inherent time delay; phased-array antennas; phased-array design; pull-in range; synchronization behavior; Circuit stability; Coupling circuits; Delay effects; Equations; Feedback; Frequency synchronization; Oscillators; Phase locked loops; Phased arrays; Tunable circuits and devices;

fLanguage

English

Journal_Title

Microwave Theory and Techniques, IEEE Transactions on

Publisher

ieee

ISSN

0018-9480

Type

jour

DOI

10.1109/TMTT.2003.808701

Filename

1191753