Design and hardware implementation of a memory efficient Huffman decoding

Author

Hashemian, Reza

Author_Institution

Dept. of Electr. Eng., Northern Illinois Univ., DeKalb, IL, USA

Volume

40

Issue

3

fYear

1994

fDate

8/1/1994 12:00:00 AM

Firstpage

345

Lastpage

352

Abstract

Hardware design of a high speed and memory efficient Huffman decoder, introduced in Hashemian (1993) is presented. The algorithm developed is based on a specific Huffman tree structure using a code-bit clustering scheme. The method is shown to be extremely efficient in the memory requirement, and fast in searching for the desired symbols. For experimental video data with code-words extended up to 13 bits, the entire memory space needed is shown to be 122 words in size, compared with normally 2¹³=8196 words memory space requirement. The design of the decoder is carried out using the Si-gate CMOS process

Keywords

CMOS integrated circuits; Huffman codes; decoding; digital signal processing chips; image coding; memory architecture; pattern recognition; search problems; table lookup; tree data structures; video equipment; video signals; Huffman tree structure; Si-gate CMOS process; code-bit clustering; code-words; design; hardware implementation; memory efficient Huffman decoding; memory requirement; search; video data; CMOS process; Clustering algorithms; Data compression; Decoding; Entropy coding; Hardware; Huffman coding; Random access memory; Table lookup; Tree data structures;

fLanguage

English

Journal_Title

Consumer Electronics, IEEE Transactions on

Publisher

ieee

ISSN

0098-3063

Type

jour

DOI

10.1109/30.320814

Filename

320814