Parallel implementation of transform-based DCT filter-bank for video communications

Author

Chiu, C.T.

Author_Institution

Dept. of Electr. Eng., Nat. Cheng Kung Univ., Tainan, Taiwan

Volume

40

Issue

3

fYear

1994

fDate

8/1/1994 12:00:00 AM

Firstpage

473

Lastpage

475

Abstract

This paper proposes a new filter bank structure based on the discrete cosine transform (DCT) and inverse DCT (IDCT) using modified autoregressive filter realization for real-time applications. The number of multipliers required in the synthesis bank is only N-1, which is the minimum number of multipliers for the IDCT compared to previous architectures. The VLSI implementations of the filter modules show that it can achieve 116 Mb/s and 540 Mb/s data rate under 2 μm and 0.8 μm CMOS SPDM technology

Keywords

CMOS integrated circuits; VLSI; digital filters; discrete cosine transforms; visual communication; 0.8 micron; 116 Mbit/s; 2 micron; 540 Mbit/s; CMOS SPDM technology; DCT filter bank; IDCT; VLSI; discrete cosine transform; filter bank structure; filter modules; inverse DCT; modified autoregressive filter; multipliers; real-time applications; synthesis bank; video communications; CMOS technology; Discrete cosine transforms; Discrete transforms; Filter bank; IIR filters; Signal processing; Signal processing algorithms; Signal synthesis; Transform coding; Very large scale integration;

fLanguage

English

Journal_Title

Consumer Electronics, IEEE Transactions on

Publisher

ieee

ISSN

0098-3063

Type

jour

DOI

10.1109/30.320830

Filename

320830