Optimization and evaluation of image- and signal-processing kernels on the TI C6678 multi-core DSP

Power efficiency is an important aspect in today´s high-performance embedded computing (HPEC) systems. Digital signal processors (DSPs) are well known for their power efficiency and are commonly employed in embedded systems. Increasing computational demands in image- and signal-processing applications in embedded systems has led to the development of multi-core DSPs with floating-point capabilities. The TMS320C6678 is an eight-core, high-performance DSP from Texas Instruments that provides 128 GFLOPS of single-precision and 32 GFLOPS of double-precision performance under 10W of power. In this paper, we optimize and evaluate the performance of the TMS320C6678 DSP using two image-processing kernels, 2D convolution and bilinear interpolation with image rotation, and two signal-processing kernels, frequency-domain finite impulse response (FDFIR) and corner turn. Our 2D convolution results show that the performance of the TMS320C6678 is comparable to a Nvidia GeForce 295 GTX GPU and 5 times better than a quad-core Intel Xeon W3520 CPU. We achieve real-time performance for bilinear interpolation with image rotation on the TMS320C6678 for high-definition (HD) image resolution. Our performance per Watt results for FDFIR shows that the TMS320C6678 is 8.2 times better than the Nvidia Tesla C2050 GPU. For corner turn, although the raw performance of the Tesla C2050 is better than the TMS320C6678, the performance per Watt of TMS320C6678 is 1.8 times better than the Tesla C2050.