Energy-efficient histogram equalization on FPGA

Histogram equalization is a common kernel used for image processing, a widely-used procedure for many present-day applications. Much of the work done emphasizes throughput and area-efficient designs, yet energy efficiency is a relatively untapped field. In this work, we develop an energy-efficient histogram equalization architecture and propose a memory activation schedule to minimize energy consumption. For larger image sizes, we design an efficient buffering and power-down scheme to reduce external DRAM power computation. Pipelining and data hazard prevention are employed to achieve a realistic frame rate of 30+ frames per second. The image sizes range from 240 × 128 to 3840 × 2160, with a width of 16 bits per pixel. We compare our results against the theoretical peak performance of histogram equalization on the target device, maintaining up to 77% of the peak performance. Post place-and-route results show that our optimized architecture achieves up to 12.8× higher energy efficiency than the baseline architecture.