Energy performance of FPGAs on PERFECT suite kernels

Author

Kuppannagari, Sanmukh R. ; Ren Chen ; Sanny, Andrea ; Singapura, Shreyas G. ; Tran, Geoffrey Phi C. ; Shijie Zhou ; Yusong Hu ; Crago, Stephen P. ; Prasanna, Viktor K.

Author_Institution

Ming Hsieh Dept. of Electr. Eng., Univ. of Southern California, Los Angeles, CA, USA

fYear

2014

fDate

9-11 Sept. 2014

Firstpage

1

Lastpage

6

Abstract

Energy efficiency as a metric has gained significant importance in the recent years. The goal of the TAPAS project is to discover and develop revolutionary approaches that will generate energy-efficient designs on embedded computing systems. One suitable target platform for implementing energy-efficient algorithms is the FPGA, due to its low power consumption, high performance and efficiency, and high degree of programmability. We develop optimizations targeted at reducing memory and communication energy dissipation on FPGAs. We design parameterized architectures for six kernels selected from the PERFECT benchmark suite, applying our memory and communication optimizations. Our optimizations demonstrate 3x to 110x energy efficiency improvement compared to baseline implementations.

Keywords

field programmable gate arrays; operating system kernels; performance evaluation; FPGA; PERFECT suite kernel; embedded computing system; energy performance; memory optimization; Computer architecture; Discrete wavelet transforms; Field programmable gate arrays; Histograms; Kernel; Optimization; Random access memory;

fLanguage

English

Publisher

ieee

Conference_Titel

High Performance Extreme Computing Conference (HPEC), 2014 IEEE

Conference_Location

Waltham, MA

Print_ISBN

978-1-4799-6232-7

Type

conf

DOI

10.1109/HPEC.2014.7041004

Filename

7041004