Title :
A 0.8 μ 100-MHz 2-D DCT core processor
Author :
Jang, Yi-Feng ; Kao, Jinn-Nang ; Yang, Jinn-Shiang ; Huang, Po-Chuang
Author_Institution :
ITRI/CCL, Hsinchu, Taiwan
fDate :
8/1/1994 12:00:00 AM
Abstract :
The discrete cosine transform (DCT) has been commonly adopted in many transformation applications such as image, video, and facsimile. A VLSI architecture and implementation of a high speed 2-dimensional DCT core processor with 0.8 μ technology is presented. This architecture applies a fast DCT algorithm and multiplier-accumulator based on the distributed algorithm, which has contributed to reduce the hardware requirement and to achieve high speed operation. The transpose memory inserted between each dimension of DCT is partitioned in order to reduce further hardware overhead. Furthermore, this 2-dimensional DCT scheme satisfies the accuracy specification of CCITT recommendation MPEG
Keywords :
CMOS integrated circuits; VLSI; carry logic; digital signal processing chips; discrete cosine transforms; memory architecture; multiplying circuits; pipeline processing; random-access storage; 0.8 μ 100-MHz 2D DCT core processor; 0.8 mum; 100 MHz; CCITT recommendation MPEG; TRAM; VLSI architecture; discrete cosine transform; distributed algorithm; facsimile; hardware requirement; high speed operation; image; multiplier-accumulator; transformation applications; transpose RAM; transpose memory; video; Discrete cosine transforms; Discrete transforms; Equations; Frequency; Matrices; Pipelines; Yttrium;
Journal_Title :
Consumer Electronics, IEEE Transactions on
