Techniques for multilayer channel routing

Author

Braun, Douglas ; Burns, Jeffrey L. ; Romeo, Fabio ; Sangiovanni-Vincentelli, Alberto ; Mayaram, Kartikeya ; Devadas, Srinivas ; Ma, Hi-keung Tony

Author_Institution

Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA, USA

Volume

7

Issue

6

fYear

1988

fDate

6/1/1988 12:00:00 AM

Firstpage

698

Lastpage

712

Abstract

The techniques described have been implemented in a multilayer channel router called Chameleon. Chameleon consists of two stages: a partitioner and a detailed router. The partitioner divides the problems into two-layer and three-layer subproblems such that global channel area is minimized. The detailed router then implements the connections using generalizations of the algorithms used in YACR2 (see ibid., vol.CAD-4, no.3, p.208-19, 1985). In particular, a three-dimensional maze router is used for the vertical connections; this methodology is effective even when cycle constraints are present. Chameleon has produced optimal results on a wide range of industrial and academic examples for a variety of layer and pitch combinations, and can handle a variety of technology constraints

Keywords

circuit layout CAD; monolithic integrated circuits; Chameleon; cycle constraints; detailed router; global channel area; multilayer channel routing; partitioner; pitch combinations; technology constraints; three-dimensional maze router; three-layer subproblems; two-layer subproblems; vertical connections; Integrated circuit interconnections; Integrated circuit layout; Macrocell networks; Manufacturing; Nonhomogeneous media; Partitioning algorithms; Pins; Printed circuits; Routing; Stacking;

fLanguage

English

Journal_Title

Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on

Publisher

ieee

ISSN

0278-0070

Type

jour

DOI

10.1109/43.3209

Filename

3209