DocumentCode
1173647
Title
Design, synthesis, and test of networks on chips
Author
Pande, Partha Pratim ; Grecu, Cristian ; Ivanov, André ; Saleh, Resve ; De Micheli, Giovanni
Author_Institution
Sch. of Electr. Eng. & Comput. Sci., Washington State Univ., Pullman, WA, USA
Volume
22
Issue
5
fYear
2005
Firstpage
404
Lastpage
413
Abstract
For networks on chips to succeed as the next generation of on-chip interconnect, researchers must solve the major problems involved in designing, implementing, verifying, and testing them. This article surveys the latest NoC architectures, methods, and tools and shows what must happen to make NoCs part of a viable future.
Keywords
logic design; logic testing; microprocessor chips; multiprocessor interconnection networks; parallel architectures; system-on-chip; NoC testing; microprocessor chip; multiprocessor interconnection network; network on chip design; parallel architecture; Bandwidth; Clocks; Delay; Network synthesis; Network-on-a-chip; Switches; Testing; Throughput; Wire; Wiring; Automatic synthesis; Reliability; Testing; VLSI; VLSI Systems; and Fault-Tolerance;
fLanguage
English
Journal_Title
Design & Test of Computers, IEEE
Publisher
ieee
ISSN
0740-7475
Type
jour
DOI
10.1109/MDT.2005.108
Filename
1511972
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