Title :
An update on IEEE P1647: the e system verification language
Author_Institution :
Dept. of Victor Berman, Cadence Design Syst., North Andover, CA, Canada
Abstract :
The e language forms the basis of an extensive set of tools and methodologies, collectively known as verification process automation, and almost all major electronics companies worldwide use it. This paper discusses IEEE design automation standards project and shows that how the value of technology can be enhanced by the standardization process.
Keywords :
IEEE standards; electronic design automation; formal verification; hardware description languages; standardisation; IEEE P1647; IEEE design automation standards; e system verification language; hardware description language; standardization; Character generation; Concurrent computing; Engineering management; Hardware design languages; Maintenance engineering; Object oriented modeling; Resource management; Scalability; System testing; Time to market; IEEE P1647; e language; functional verification; standardization; verification; verification process automation;
Journal_Title :
Design & Test of Computers, IEEE
DOI :
10.1109/MDT.2005.102
