Shallow buried channel gated BJT on TFSOI substrate

Author

Chen, V.M.C. ; Woo, J.C.S.

Author_Institution

Dept. of Electr. Eng., California Univ., Los Angeles, CA, USA

Volume

15

Issue

10

fYear

1994

Firstpage

391

Lastpage

393

Abstract

The gated BJT structure is inherently suitable for SOI BiCMOS technology. However, being a surface channel device, it suffers higher noise and degraded carrier transport. In this study, a novel shallow buried channel design on TFSOI is proposed. Devices with various geometries have been fabricated with a simple CMOS-compatible process. These devices have low turn-on voltage, ideal BJT I-V characteristics with current gain higher than 1000, and a maximum transconductance of 290 mS/mm for a 0.5 μm channel length and 15 nm gate oxide. Careful measurements show that an order of magnitude improvement in noise performance can be expected from the buried channel operation. These devices are suitable for various BiCMOS applications.

Keywords

BiCMOS integrated circuits; bipolar transistors; integrated circuit technology; semiconductor-insulator boundaries; silicon; 0.5 micron; 290 mS/mm; CMOS-compatible process; I-V characteristics; SOI BiCMOS technology; Si; gated BJT structure; shallow buried channel design; thin film SOI substrate; BiCMOS integrated circuits; CMOS technology; Degradation; Electrons; Geometry; Implants; Low voltage; Oxidation; Substrates; Transconductance;

fLanguage

English

Journal_Title

Electron Device Letters, IEEE

Publisher

ieee

ISSN

0741-3106

Type

jour

DOI

10.1109/55.320978

Filename

320978