Title :
A vertical submicron polysilicon thin-film transistor using a low temperature process
Author :
Tiemin Zhao ; Min Cao ; Saraswat, K.C. ; Plummer, J.D.
Author_Institution :
Center for Integrated Syst., Stanford Univ., CA, USA
Abstract :
This letter presents a submicron (0.5 μ) vertical N-channel MOS thin-film transistor (TFT) fabricated in Polycrystalline Si using a simple low temperature process (/spl les/600/spl deg/C). The channel length is determined by the thickness of an SiO2 film. As a result, submicron vertical polysilicon TFT´s can be fabricated without submicron lithographic equipment that is not yet available for large area active matrix liquid crystal display (AMLCD) applications. The device has a dynamic range of greater than five orders of magnitude after hydrogenation.
Keywords :
elemental semiconductors; large screen displays; liquid crystal displays; low-temperature techniques; semiconductor technology; silicon; thin film transistors; 0.5 micron; 600 degC; AMLCD; Si-SiO/sub 2/; channel length; dynamic range; hydrogenation; large area active matrix liquid crystal display; low temperature process; polysilicon thin-film transistor; vertical N-channel MOS TFT; Active matrix liquid crystal displays; Amorphous materials; Crystallization; Etching; Lithography; Semiconductor films; Silicon; Substrates; Temperature; Thin film transistors;
Journal_Title :
Electron Device Letters, IEEE
