Title :
Hardware Reduction in Digital Delta–Sigma Modulators Via Error Masking—Part II: SQ-DDSM
Author :
Ye, Zhipeng ; Kennedy, Michael Peter
Author_Institution :
Dept. of Microelectron. Eng., Univ. Coll. Cork, Cork
Abstract :
In this two-part paper, a design methodology for reduced-complexity digital delta-sigma modulators (DDSMs) based on error masking is presented. Rules for selecting the wordlengths of the stages in multistage architectures are elaborated. We show that the hardware requirement can be reduced by up to 20% compared with a conventional design, without sacrificing performance. Simulation results confirm theoretical predictions. Part I addresses multistage noise-shaping DDSMs, whereas Part II focuses on single-quantizer DDSMs.
Keywords :
delta-sigma modulation; integrated circuit noise; digital delta-sigma modulator; error masking; hardware reduction; multistage architecture; multistage noise-shaping; single-quantizer DDSM; Delta modulation; Delta-sigma modulation; Design methodology; Digital modulation; Hardware; Microelectronics; Multi-stage noise shaping; Noise shaping; Quantization; Topology; Delta–sigma modulator; error masking; reduced complexity;
Journal_Title :
Circuits and Systems II: Express Briefs, IEEE Transactions on
DOI :
10.1109/TCSII.2008.2010188
