DocumentCode :
1174135
Title :
Flash ADC architecture
Author :
Stojcevski, A. ; Le, H.P. ; Singh, J. ; Zayegh, A.
Author_Institution :
Sch. of Commun. & Informatics, Victoria Univ., Melbourne, Vic., Australia
Volume :
39
Issue :
6
fYear :
2003
fDate :
3/20/2003 12:00:00 AM
Firstpage :
501
Lastpage :
502
Abstract :
A 4-bit, 2.5 V modified flash analogue-to-digital converter (ADC) has been designed. In this design, the new flash topology only requires 2(N-2)+2 comparators. For comparison reasons, this new ADC architecture is operated at 400 MHz, consumes a total power of 1.68 mW and generates a total noise power of 4.86×10-15. Δf(V2) at this frequency.
Keywords :
analogue-digital conversion; comparators (circuits); integrated circuit noise; 1.68 mW; 2.5 V; 4 bit; 400 MHz; ADC; comparators; flash analogue-to-digital converter; flash topology; high-speed converter; total noise power; total power;
fLanguage :
English
Journal_Title :
Electronics Letters
Publisher :
iet
ISSN :
0013-5194
Type :
jour
DOI :
10.1049/el:20030290
Filename :
1192193
Link To Document :
https://search.ricest.ac.ir/dl/search/defaultta.aspx?DTC=49&DC=1174135
بازگشت