Realizing high-voltage junction isolated LDMOS transistors with variation in lateral doping

Author

Hardikar, Shyam ; Tadikonda, Ramakrishna ; Green, David W. ; Vershinin, Konstantin V. ; Narayanan, Ekkanath Madathil Sankara

Author_Institution

Emerging Technol. Res. Centre, De Montfort Univ., Leicester, UK

Volume

51

Issue

12

fYear

2004

Firstpage

2223

Lastpage

2228

Abstract

High-voltage lateral diffused metal-oxide semiconductor (LDMOS) transistors with a variation in the lateral doping (VLD) of drift regions are demonstrated in junction isolation technology using a fully implanted CDMOS process. The VLD profile is realized by using an analytical approach reported previously. The analytical model is verified through simulations and experiment. Results indicate that higher breakdown voltages can be achieved for a given drift length using a VLD profile in comparison to uniform doping while offering a good tradeoff between breakdown voltage and specific on-resistance.

Keywords

MOSFET; circuit simulation; doping profiles; power integrated circuits; VLD profile; breakdown voltage; breakdown voltages; drift length; drift regions; fully implanted CDMOS process; high-voltage integrated circuits; high-voltage junction isolated LDMOS transistors; junction isolation technology; lateral diffused metal-oxide semiconductor transistors; lateral doping; power integrated circuit; reduced surface field; Analytical models; Circuit simulation; Doping profiles; Isolation technology; MOSFET circuits; Power integrated circuits; Programmable control; Semiconductor device doping; Silicon on insulator technology; Voltage; 211;oxide semiconductor; 65; HVIC; High-voltage integrated circuits; LDMOS; RESURF; VLD; junction isolation; lateral diffused metal&#; power ICs; reduced surface field; variation in lateral doping;

fLanguage

English

Journal_Title

Electron Devices, IEEE Transactions on

Publisher

ieee

ISSN

0018-9383

Type

jour

DOI

10.1109/TED.2004.839104

Filename

1362992