Optimisation techniques for reducing global bus switching activity in realisations of sum-of-products computations in DSP systems

Optimisation techniques aiming at the reduction of power consumption in digital signal processing (DSP) systems are presented. These optimisation techniques hold for all algorithms, including sum-of-products computations between input data and coefficients, which is a very broad category of DSP algorithms. Power savings are obtained through the reduction of switching activity in both (input and coefficient) data and address buses of the hardware architecture implementing the algorithm. The reduction of switching activity is obtained by means of a shuffling of the sequence, in which the partial products required by the sum-of-products computations are executed. The optimisation problems are formulated as travelling salesman problem (TSP) instances, which is a well known NP-complete problem. The cost function that drives the optimisation process takes explicitly into consideration addressing-related issues, which is not the case in existing approaches dealing with the same problem. Experimental results show that the proposed techniques achieve significant switching activity savings, resulting in corresponding power savings, while ensuring that no penalties are introduced in the address buses.