An efficient structure of carry select adder

Carry select adder is fastest adder but it required more area and power. The modern VLSI design systems are small in size and less power consumption so the modification is need in the carry select adder to achieve the reduced area and less power consumption. Two proposed works are introduced in thispaper. First method include the reduction of area and power in Carry select adder by modifying the EX-OR gate and BINARY TO EXCESS converter. Modification of Ex-or gate is done inside the RIPPLE CARRY ADDER. Second method includes the reduction of delay by replacing CARRY LOOK AHEAD instead of Ripple carry adder. This replacement increases the area, this can be overcome by modifying the EX-OR gate in CARRY LOOK AHEAD block.