An advanced low complexity double error correction of an BCH decoder

Bose, Ray-Chaudhuri, Hocquenghem (BCH) codes are one of the efficient error-correcting codes used to correct errors occurred during the transmission of the data in the unreliable communication mediums. This paper presents a low-complexity and area efficient error-correcting BCH decoder architecture for detecting and correction of two errors. The advanced Peterson error locator computation algorithm, which significantly reduces computational complexity, is proposed for the IBM block in the BCH decoder. In addition, a modified syndrome calculator and chien search are proposed to reduce hardware complexity. The proposed model and design techniques have considerably less hardware complexity and latency than those using conventional algorithms. For a (15,7) BCH decoder over GF(4), the proposed design can lead to a reduction in complexity of at least 30 % compared to conventional architectures. The enhanced chase BCH decoder is designed using hardware description language called Verilog and synthesized in Xilinx ISE 13.2.