Interconnect matrix for multichannel AMBA AHB with multiple arbitration technique

The on chip bus plays key role in the system on chip design by enabling the efficient integration of heterogeneous system component like CPUs, DSPs, application specific cores, memories, custom logic. As the level of design complexity has become higher, soc design requires a system bus with high bandwidth to perform the multiple operations in parallel. There has been several type of high performance on chip buses proposed to solve the bandwidth problem such as multichannel AHB busmatrix in ARM, the PLB crossbar switch in IBM, and CONMAX in silicore. Among them multichannel AHB busmatrix have been widely used in many SOC designs. This is because the simplicity of AMBA BUS of ARM, which attracts many IP designers and good architecture of the AMBA bus for applying embedded system with low power. In this project, we implemented multichannel AMBA AHB with its multiple arbitrations techniques such as round robin, fixed priority. AMBA AHB is basically single layer bus. In this project we implement and design the interconnect matrix for single layer amba ahb which includes four masters and four slaves. The design of flexible centre arbiter for flexible busmatrix supports the different priority policies such as round robin, fixed priority, dynamic arbitration. In this, we also design the new arbiter which removes the dynamic arbiter disadvantages. In this new arbiter we combine the round robin and dynamic arbiter. The design of single layer AMBA AHB includes all the AMBA AHB signals or specifications. We designed and implemented this by using xillinx simulators and by using FPGA (SPARTAN) because this provides flexibility and high density.