DocumentCode
1175479
Title
Designing fault-tolerant techniques for SRAM-based FPGAs
Author
De Lima Kastensmidt, Fernanda Gusmão ; Neuberger, Gustavo ; Hentschke, Renato Fernandes ; Carro, Luigi ; Reis, Ricardo
Author_Institution
Dept. of Digital Syst. Eng., State Univ. of Rio Grande do Sul, Guaiba, Brazil
Volume
21
Issue
6
fYear
2004
Firstpage
552
Lastpage
562
Abstract
FPGAs have become prevalent in critical applications in which transient faults can seriously affect the circuit´s operation. We present a fault tolerance technique for transient and permanent faults in SRAM-based FPGAs. This technique combines duplication with comparison (DWC) and concurrent error detection (CEO) to provide a highly reliable circuit while maintaining hardware, pin, and power overheads far lower than with classic triple-modular-redundancy techniques.
Keywords
SRAM chips; combinational circuits; error detection; fault tolerance; field programmable gate arrays; logic design; logic testing; FPGA; SRAM; circuit operation; concurrent error detection; duplication with comparison; fault-tolerant techniques; transient faults; triple-modular-redundancy techniques; Circuit faults; Clocks; Delay; Fault tolerance; Field programmable gate arrays; Integrated circuit interconnections; Logic devices; Programmable logic arrays; Routing; Table lookup;
fLanguage
English
Journal_Title
Design & Test of Computers, IEEE
Publisher
ieee
ISSN
0740-7475
Type
jour
DOI
10.1109/MDT.2004.85
Filename
1363710
Link To Document