DocumentCode
1175487
Title
Enhancing yield at the end of the technology roadmap
Author
Sirisantana, Naran ; Paul, Bipul C. ; Roy, Kaushik
Volume
21
Issue
6
fYear
2004
Firstpage
563
Lastpage
571
Abstract
Scaled manufacturing technologies require advanced techniques for improving device reliability and production yield. We present a transistor-level redundancy technique for manufacturing devices with low vulnerability and improving yield in future circuits The technique relies on appropriate design style selection and controlled redundancy to achieve area and power trade-offs.
Keywords
CMOS integrated circuits; integrated circuit manufacture; integrated circuit reliability; logic circuits; logic design; logic testing; redundancy; manufacturing devices; roadmap technology; scaled manufacturing technology; transistor-level redundancy technique; Circuit faults; Circuit noise; Circuit testing; Design methodology; Fault tolerance; Manufacturing industries; Power amplifiers; Production; Redundancy; Semiconductor device measurement;
fLanguage
English
Journal_Title
Design & Test of Computers, IEEE
Publisher
ieee
ISSN
0740-7475
Type
jour
DOI
10.1109/MDT.2004.86
Filename
1363711
Link To Document