Title :
System-level design language standard needed
Author_Institution :
Cadence Design Syst., North Andover, MA, USA
Abstract :
The combination of SystemVerilog, SystemC, and the property specification language (PSL) promises a powerful and flexible foundation for design. Together, these standards address clear needs for emerging software-rich designs; critical capabilities for these standards include advanced verification features such as solvers and constrained random testing. This combination of standards brings powerful assertion capabilities that, with PSL, provide a bridge to formal verification and the ability to apply assertions across multiple design languages.
Keywords :
formal verification; hardware description languages; logic design; logic testing; system-on-chip; SystemC; SystemVerilog; constrained random testing; formal verification; property specification language; software-rich design; system-level design language standard; Bridges; Computational modeling; Design engineering; Heart; Power engineering and energy; Power system modeling; System testing; System-level design; Systems engineering and theory;
Journal_Title :
Design & Test of Computers, IEEE
DOI :
10.1109/MDT.2004.98
