DocumentCode :
117554
Title :
Design and implementation of area efficient, low power AMBA-APB Bridge for SoC
Author :
Paunikar, Abhijeet ; Gavankar, Rohan ; Umarikar, Nachiket ; Sivasankaran, K.
Author_Institution :
Sch. of Electron. Eng., VIT Univ., Vellore, India
fYear :
2014
fDate :
6-8 March 2014
Firstpage :
1
Lastpage :
6
Abstract :
In this paper, we present the design of Advanced Peripheral Bus (APB) controller (or APB Bridge). UART as an APB slave has been used in the design. Linear Feedback shift register (LFSR) module has been included in the UART design for data security. We have also compared APB Bridge design compatible with AMBA Specification (Rev 2.0) and APB Bridge design compatible with AMBA 3 APB Specification (v1.0) for power and area constraints have been done. Design of APB Bride with AMBA3 APB save 6% power and 10% area over the one designed with AMBA2 APB.
Keywords :
bridge circuits; integrated circuit interconnections; low-power electronics; security of data; shift registers; system-on-chip; AMBA 3 APB specification; LFSR; UART design; advanced peripheral bus controller; data security; linear feedback shift register; low power AMBA-APB bridge; system-on-chip; Bridge circuits; Bridges; Receivers; Shift registers; Synchronization; System-on-chip; Transmitters; Advanced Microcontroller Bus Architecture (AMBA); Advanced Peripheral Bus (AMBA APB); Intellectual Property (IP); System-on-Chip (SOC); Universal Synchronous Transmitter Receiver (UART);
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Green Computing Communication and Electrical Engineering (ICGCCEE), 2014 International Conference on
Conference_Location :
Coimbatore
Type :
conf
DOI :
10.1109/ICGCCEE.2014.6922239
Filename :
6922239
Link To Document :
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