VLSI design of low power SRAM architectures for FPGAs

SRAM cell, a semi-conductor memory, is majorly used to store/retrieve time independent data. SRAM cells of various configurations with proper understanding of their functioning are mentioned in this study. Typically, an SRAM cell uses six MOSFETS while various architectures for the cells are also available with the number of transistors ranging from 4 to 12 and more. The architectures are different from each other with respect to parameters such as data retention stability, area, power dissipation, feature size. With the size of designs scaling down drastically, the power consumption is tending to be an issue and this study involves difference design architectures of low power SRAM cells. Electronic computer aided design software tools like Digital Schematic editor and the Microwind layout editor are used to obtain the required simulation results.