Title :
Function-based compact test pattern generation for path delay faults
Author :
Michael, Maria K. ; Tragoudas, Spyros
Author_Institution :
Dept. of Electr. & Comput. Eng., Univ. of Cyprus, Nicosia, Cyprus
Abstract :
We present a function-based nonenumerative automatic test pattern generation (ATPG) methodology for detecting path delay faults (PDFs). The proposed technique consists of a number of topological circuit traversals during each a linear number of Boolean functions is generated per circuit line. From each such function we derive a test that detects many PDFs. The two major strengths of the approach, that stem from the function-based formulations used, are very compact test sets, and scalability in test efficiency. The performance of an implementation based on binary decision diagrams is evaluated and compared with existing compact methods to demonstrate the superiority of the proposed method.
Keywords :
Boolean functions; automatic test pattern generation; binary decision diagrams; fault diagnosis; ATPG; Boolean function; Boolean/algebraic test generation; PDF; automatic test pattern generation; binary decision diagram; path delay fault; test compaction; test efficiency; Automatic test pattern generation; Boolean functions; Circuit faults; Circuit testing; Data structures; Delay; Electrical fault detection; Fault detection; Scalability; Test pattern generators; Automatic test pattern generation (ATPG); Boolean/algebraic test generation; binary decision diagram (BDD); delay faults; nonenumerative; test compaction; test efficiency; testing;
Journal_Title :
Very Large Scale Integration (VLSI) Systems, IEEE Transactions on
DOI :
10.1109/TVLSI.2005.853607