Design of a systolic array based multiplierless support vector machine classifier

This paper presents design of a multiplierless kernel operation for binary Support Vector machine which is based on systolic array architecture. This design provides reduced area, reduced cost and high speed performance due to the use of multiplierless kernel operation. Binary SVM classifier classifies two groups of linearly or nonlinearly separable data. We have designed an algorithm which is expected to reduce area, reduce power and speed up the processor in hardware level. At first SVM classifier is trained and then extracted training parameters are used in the testing phase of the same. The dataflow from all the processing elements (PE) s is parallely supported by systolic array.