DS CDMA multiuser receiver employing multiple access interference cancellation using iterative demodulator architecture

An implementation of iterative joint detection for multiple access interference using direct-sequence code division multiple access is presented. Results for multiple field programmable gate array (FPGA) and multiple technology nodes for synthesized application specific integrated circuits (ASIC) are presented. The joint detection is based on iterative cancellation known as partition spreading (PS) CDMA. In joint detection architecture the channel interleaver is proposed to increase the data rate and reduce the area. The synthesized ASIC system demonstrates a maximum aggregate throughput of 195Mb/s for 50 user system, while the implemented FPGA 50 users system has a maximum aggregate throughput of 119Mb/s.