DocumentCode :
117657
Title :
An improved gate capacitance for two dimensional junctionless transistor
Author :
Kumar, B. Pradeep ; Amarnath, G. ; Arif, Wasim ; Baishya, S.
Author_Institution :
Nat. Inst. of Technol., Silchar, India
fYear :
2014
fDate :
6-8 March 2014
Firstpage :
1
Lastpage :
3
Abstract :
The junctionless transistor is one of the device structures which found tremendous potential in terms of reduction of short channel effects, scaling factors, capacitance & fabrication. In this paper we observed an improved gate capacitance (Cgg) in depletion and inversion regions of a T-shape double gate junctionless transistor with comparison to the single gate junctionless transistor for different oxide thickness (tox), doping concentration (ND) and Gate lengths (Lg).
Keywords :
MOSFET; doping profiles; semiconductor device models; T-shape double gate junctionless transistor; depletion region; doping concentration; gate capacitance; gate length; inversion region; oxide thickness; short channel effects; single gate junctionless transistor; Capacitance; Doping; Logic gates; MOSFET; Semiconductor process modeling; Silicon; Gate length; Junctionless transistor; doping concentration; gate capacitance;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Green Computing Communication and Electrical Engineering (ICGCCEE), 2014 International Conference on
Conference_Location :
Coimbatore
Type :
conf
DOI :
10.1109/ICGCCEE.2014.6922275
Filename :
6922275
Link To Document :
https://search.ricest.ac.ir/dl/search/defaultta.aspx?DTC=49&DC=117657
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